CSCI 3500: Studio 17

Translation Lookaside Buffer (TLB)

The translation lookaside buffer (TLB) is a special hardware cache that speeds up accesses to a process' page table. Even though a process can theoretically access its full virtual memory space, most processes access much less. The princple of the TLB is that, ideally, most programs will only access a very small subset of their total space. If all pages can be kept in the TLB, then memory accesses will be very fast.

In this studio, you will:

  1. Analyze TLB function
  2. Analyze TLB effect

Please complete the required exercises below, as well as any optional enrichment exercises that you wish to complete.

As you work through these exercises, please record your answers in a text file. When finished, submit your work by sending your text file and source code to dferry_submit@slu.edu with the phrase TLB in the subject line.

Make sure that the name of each person who worked on these exercises is listed in the first answer, and make sure you number each of your responses so it is easy to match your responses with each exercise.

Required Exercises

  1. As the answer to the first exercise, list the names of the people who worked together on this studio.

    For the following exercises, consider the following page table. Suppose a page size of 1024 bytes:

    Page
    (in binary)    		 Page Frame
    (in binary)    		 Valid Modified Permissions
    0000 10011 1 1 r
    0001 10100 1 1 rw
    0010 00101 1 0 rx
    0011 10111 1 1 rw
    0100 00000 0 0 rw
    0101 00110 0 0 rx

    Furthermore, suppose this machine has a TLB with the following contents:

    Page
    (in binary)    		 Page Frame
    (in binary)    		 Referenced Modified Permissions
    0001 10100 1 1 rw
    0010 00101 1 0 rx
    0101 00110 0 0 rx

  2. Does an access to the virtual address 00110011110011 cause a TLB hit?

  3. Does an access to the virtual address 00010011001110 cause a TLB hit?

  4. Like page frames in physical memory, the system has to have a policy for evicting entries in the TLB when it needs to make room for a new entry. Recall the Not Recently Used (NRU) page replacement policy, which is an approximxation of the Least Recently Used (LRU) policy. Under NRU, pages are evicted in the order of class:

    Class 0 - not referenced, not modified
    Class 1 - not referenced, modified
    Class 2 - referenced, not modified
    Class 3 - referenced, modified

    Under the NRU policy, which page in the page table would be evicted next?

  5. Which three pages remain in the TLB after the following memory accesses? Assume the TLB starts in the configuration presented above, and that it uses the NRU replacement policy. New pages start with the referenced bit set to one.

    00110010010000 - read
    00100000111011 - read
    00110000101110 - read
    00110000010101 - write
    00010001000010 - write
    01100000100001 - read
    01010010011100 - read

  6. Suppose you're a computer engineer tasked with designing a chip's TLB. You write a program to simulate a basic TLB as though it ran a program with 100000 memory accesses. You assume that when a memory access hits in the TLB it will take 1 cycle, but when an access misses it will take 30 cycles.

    In your first design you hit 90% of the time and miss 10% of the time- that is, you have 10,000 TLB misses and 90,000 TLB hits. How many cycles does your program spend on TLB misses? How many cycles does it spend on TLB hits? How many total cycles does your program spend on memory accesses?

  7. What is the average number of cycles spent on memory accesses? (Total number of cycles divided by number of accesses.)

  8. You have a budget to improve your TLB, so you can't make everything great. You come up with two improved designs.

    In your first plan, you're able to reduce the TLB miss time from 30 cycles to 20 cycles. Given the same program as above, how many total cycles does the program spend on memory accesses? What is the average number of cycles per access?

  9. For your second alternative, you're able to reduce the TLB miss rate from 10% to 1%. That is- you have 1,000 TLB misses and 99,000 TLB hits. How many cycles does your program spend on memory accesses? What is the average number of cycles per access?

  10. Which design is better? By how many cycles? How much better is it as a ratio?

Optional Enrichment Exercises

  1. No optional exercises