Contents:

• Overview
• Problems to be Submitted

Topics: Cache Memory Organization and Operation
Related Reading: Section 5.3 of zyBooks and class notes

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You are allowed to submit your assignment via email, but if you choose to do so, you must bring a hardcopy of your assignment along with a completed cover sheet to the instructor at the next class. (Note: Do not email the instructor any .zip file attachments, as SLU's email may not accept these emails; i.e. the instructor may not receive your email.)

1.   (5 points)

   Shown below are five different cache configurations. In each case, you are given the following:

   • P ‐  the amount of physical memory
   • C ‐  the size (capacity) of the cache
   • B ‐  the block size, in bytes, of blocks within the cache
   • K ‐  the associativity of the cache

   Given these values, you are asked to complete the table, computing the following for each of the five cache configurations:

   • N ‐  the number of sets in the cache
   • t ‐  the number of tag bits
   • s ‐  the number of set bits
   • b ‐  the number of block offset bits

   

2.   (7 points)

   Shown below are two cache problems, 6.31 and 6.32, from another book. Given these, please complete the following:

   1.   (1 pt)   Complete Problem #6.31
   2.   (2 pts)   Complete Problem #6.32
   3.   (2 pts)   Repeat Problem #6.32 for the address 0x1315
   4.   (2 pts)   Repeat Problem #6.32 for the address 0x0FF0

   Note:  For reference, here’s the result of a few sample addresses:

   • Address 0x178E maps to set #3, and has a tag of 0xBC. The fourth block in the set has a tag of 0xBC, but it’s valid bit is 0, so address 0x178E results in a cache miss.
   • Address 0x283 maps to set #0, and has a tag of 0x14. The third block in the set has a tag of 0x14, and it’s valid bit is 1, so address 0x283 results in a cache hit. Based on the block offset bits, the cache returns the byte with value 0x2A.